ADS8329 Verilog fpga 驱动源码，2.7V 至 5.5V 16 位 1MSPS 串行模数转换器 ADC芯片ADS8329数据采集的verilog代码，已经用在工程中，可以做为你的设计参考。
(
input clock,
input timer_clk_r,
input reset,
output reg sample_over,
output reg ad_convn,
input ad_eocn,
output reg ad_csn,
output reg ad_clk,
input ad_dout,
output reg ad_din,
output reg [15:0] ad_data_lock
);
reg [15:0] ad_data_old;
reg [15:0] ad_data_new;
reg [19:0] ad_data_temp;
reg [15:0] ad_data;
reg [4:0] ad_data_cnt;
reg [4:0] ad_spi_cnt;
reg [5:0] time_dly_cnt;
parameter [3:0] state_mac_IDLE = 0,
state_mac_0 = 1,
state_mac_1 = 2,
state_mac_2 = 3,
state_mac_3 = 4,
state_mac_4 = 5,
state_mac_5 = 6,
state_mac_6 = 7,
state_mac_7 = 8,
state_mac_8 = 9,
state_mac_9 = 10,
state_mac_10 = 11,
state_mac_11 = 12,
state_mac_12 = 13,
state_mac_13 = 14,
state_mac_14 = 15;
reg [3:0] state_curr;
reg [3:0] state_next;
