AVR IP core writen in VHDL. It is beta version, working even with AVR studio
资源简介:AVR IP core writen in VHDL. It is beta version, working even with AVR studio
上传时间: 2013-12-22
上传用户:wcl168881111111
资源简介:8051 core writen in VHDL, fully functional and tested
上传时间: 2014-01-24
上传用户:zl5712176
资源简介:USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
上传时间: 2013-11-25
上传用户:问题问题
资源简介:USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
上传时间: 2014-11-05
上传用户:lizhizheng88
资源简介:USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
上传时间: 2013-12-30
上传用户:wfeel
资源简介:USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
上传时间: 2014-11-28
上传用户:宋桃子
资源简介:USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
上传时间: 2017-03-12
上传用户:Andy123456
资源简介:This a calculator simulation program written in Labview. It is based on event structure introduced by Labviw 8.0 or later editions.
上传时间: 2015-12-27
上传用户:123456wh
资源简介:about how to develop network program in linux, it is a good start for those who want quickly to have a insight about linux network program
上传时间: 2016-01-20
上传用户:dsgkjgkjg
资源简介:this is a source code made in powerbuilder, it is very useful
上传时间: 2016-03-13
上传用户:wyc199288
资源简介:AVR IP CORE 可以直接用于工程的开发和 已经通过编译和仿真
上传时间: 2013-12-09
上传用户:黑漆漆
资源简介:DTNSim2 is a simulator for Delay-Tolerant Networks (DTNs) written in Java. It is based on Sushant Jain s DTNSim, which was used for the Routing in a delay tolerant network paper. It has been exensively modified.
上传时间: 2016-11-06
上传用户:tianyi223
资源简介:Cross street lights driver in VHDL. It have been tested on XILINX 9500.
上传时间: 2017-03-24
上传用户:gengxiaochao
资源简介:the reference of java spring in chinese , it is useful for spring study. just try to read.
上传时间: 2013-12-20
上传用户:chenxichenyue
资源简介:Convolution taking algorithm written in matlab. It is basic and so simple. Can be understood by everybody.
上传时间: 2017-06-29
上传用户:lz4v4
资源简介:RC4 SourceCode In C.it is a symetric algorithm
上传时间: 2014-12-02
上传用户:wfl_yy
资源简介:this a book about altera fpga device choice ,it is good for developing eda with fpga
上传时间: 2015-11-12
上传用户:wendy15
资源简介:This the OXO example code plus the presentation. It is intended to provide you with some clues about the structure and classes you may need for your second assignment. I have also included the jar file.
上传时间: 2016-06-20
上传用户:恋天使569
资源简介:it is a OFDM and QAM with dynamically X-QAM mdoulation scheme.
上传时间: 2017-03-22
上传用户:GHF
资源简介:Mathematic Pascal problems. it is a lil bit easy with a triangle structure. and the number inside.
上传时间: 2013-12-11
上传用户:清风冷雨
资源简介:it is a basic java player with playlist facility
上传时间: 2014-11-02
上传用户:zxc23456789
资源简介:This is our version of tetris, with "guidelines" as an option. These will allow you to easily se where the pieces will fall, be highlighing the columns that the falling piece is at the given moment. Enjoy!
上传时间: 2013-12-17
上传用户:520
资源简介:I ve written some many years ago dynamic Huffman algorithm to compress and decompress data. It is mainly targeted to data with some symbols occuring more often than the rest (e.g. having some data file consisted of 3 different symbols and t...
上传时间: 2016-05-16
上传用户:aysyzxzm
资源简介:A software input panel, a virtual keyboard for windows mobile/PocketPC. It is a undochable floating SIP with only numeric input for calculators etc.. Uses bitmap buttons.
上传时间: 2013-12-26
上传用户:wangchong
资源简介:free hardware ip core about sparcv8,a soc cpu in vhdl
上传时间: 2015-11-10
上传用户:xsnjzljj
资源简介:8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.
上传时间: 2013-12-16
上传用户:gdgzhym
资源简介:The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP core) in a VHDL simulation environment. The core is packaged as a soft (VHDL) macro and it implements all transcenden-tal functions. Analysis of...
上传时间: 2016-02-16
上传用户:wcl168881111111
资源简介:This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
上传时间: 2013-12-21
上传用户:gonuiln
资源简介:HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP ...
上传时间: 2017-06-25
上传用户:皇族传媒
资源简介:jamod is an object oriented implementation of the Modbus protocol, realized 100 in Java. It allows to quickly realize master and slave applications in various transport flavors (IP and serial).
上传时间: 2017-07-17
上传用户:LouieWu