library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( clk : in std_logic;
resetn : in std_logic;
dout : out std_logic_vector(7 downto 0);
lcd_en : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic);
end counter;
